Memory device, memory managing method and program

ABSTRACT

A memory device, performs fast data renewal and erasure, and is not easily degraded. In the memory area of a flash memory, each block is divided into physical pages and each physical pages is divided into logical pages. A redundancy portion is provided for each physical page. When supplied with to-be-written data and the logical address of a write destination, a CPU writes this data in an empty logical page and allocates the supplied logical address to this logical page. An old data flag in the redundancy portion in that physical page which includes a logical page having old data stored therein is changed in such a way as to indicate that data in this logical page is invalid. New data writing is done in that logical page to which a logical address is not allocated. At the time of flash-erasing a block, data which is stored in that logical page which is indicated by the old data flag is not transferred.

TECHNICAL FIELD

The present invention relates to a memory device, a memory managingmethod and a program, and, more particularly, to a block erasure typememory device, and a memory managing method and a program which manage ablock erasure type memory device.

BACKGROUND ART

In addition to a hard disk unit and a floppy (registered trademark)disk, an EEPROM (Electrically Erasable/Programmable Read Only Memory)flash memory is used as a recording medium which is accessible (datareadable and erasable) by a computer or the like. In case where a flashmemory is used to store files under the control of a disk operatingsystem, such as MS-DOS (registered trademark) or Windows (registeredtrademark), each of which is a product of Microsoft Corporation, thecontrol becomes easy if a scheme using data read/write units (e.g., 512bytes), which has conventionally been used at the time of using a harddisk unit, is employed.

The unit of the memory capacity of a flash memory in case where data isread or written (this unit being generally called “page” or “sector”) islarger than the unit of the memory capacity in case of erasing data (thelatter unit being generally called “block”). In case of storing data,the logic state of memory units (cells) can be changed only in onedirection (e.g., in the direction from “1” to “0”) and setting thememory units to the initial state (e.g., “1”) requires an operation toerase the memory contents block by block (flash erase).

In case of renewing or erasing data stored in the flash memory,therefore, that data in a block containing data to be renewed which isnot to be renewed is transferred to another block first. Then, the blockcontaining data to be renewed is flash-erased or renewed data is writtenin that block.

Of flash memories, particularly, a NAND type has a difficulty insufficiently preventing the occurrence of defective blocks which cannotcarry out the proper data storage at the manufacturing stage. To copewith the difficulty of the conventional flash memory, therefore,consecutive logical addresses separate from physical addresses allocatedto the respective blocks are dynamically allocated to proper blocks andan address translation table which shows the correlation between thephysical addresses and the logical addresses is prepared to avoidcomplication of external access procedures which may be originated fromaddresses becoming discontiguous.

In case of renewing or erasing data stored in the flash memory,conventionally, all the pieces of data in a block containing data to berenewed or erased were read out. Therefore, data reading took time,which would eventually make the time needed to rewrite or erase datavery long as a whole.

In case of rewriting a file whose amount of data is very small ascompared with the memory capacity for one block, the flash memoryflash-erases a block that contains lots of pages which store datairrelevant to the file and pages which are not holding data. While aNAND type flash memory can achieve a large-capacity structure at a lowcost, it would be too degraded to perform proper data reading andwriting by repetitive flash erase.

Therefore, the execution of the aforementioned operation rewrites asmall amount of data, which results in inefficient frequent flash erase.This quickens the degrading of the flash memory.

Particularly, the memory capacity of the flash memory larger has becomevery huge to increase the memory capacity per page and the memorycapacity per block considerably larger; for example, the memory capacityhas increased to about two Kbytes per page or about 128 Kbytes perblock.

Further, the increased memory capacity of the flash memory increases thecase where the memory capacity which is physically equivalent to onepage (hereinafter called “physical page”) is virtually divided intoplural memory areas (hereinafter called “logical pages”) and is used inthat form. In case where a physical page is divided into plural logicalpages and is used in that form, even when data to be renewed or eraseddoes not amount to one physical page, a block which holds this data iserased.

This further calls for the need for prevention of inefficient flasherase.

DISCLOSURE OF INVENTION

The invention has been made in consideration of the above-describedsituations and aims at providing a memory device which performs fastdata renewal and erasure and a memory managing method which executesfast renewal and erasure of data stored in a memory device.

It is another object of the invention to provide a memory device whichis not easily degraded and a memory managing method which makes thedegrading of a memory device harder.

To achieve the objects, a memory device according to the first aspect ofthe invention comprises:

a memory (11) including a plurality of memory blocks which stores dataand each of which is comprised of one or more physical pages eachincluding one or more logical pages; and

a controller (12, S314, S308 to S310) which, when to-be-written data issupplied to the memory device, writes the to-be-written data in thatempty logical page in the logical pages which is in a data storablestate, discriminates whether to-be-replaced data to be replaced with theto-be-written data is stored in the logical pages, and writes validitydata indicating that the to-be-replaced data is not valid in thatphysical page which includes the logical page that stores theto-be-replaced data, when having discriminated that the to-be-replaceddata is stored in the logical page.

In the memory device, to-be-replaced data (old data before renewal incase of renewing data) is indicated as invalid by the validity datainstead of being erased. Therefore, inefficient flash erase need not beperformed on memory blocks at the time of renewal, thus suppressing thedegrading of the memory device.

Further, the location of invalid data is specified by referring to thevalidity data. Even if reading of data in a logical page indicated bythe validity data is omitted in case of erasing the memory contents of amemory block, it is possible to properly erase the invalid data whilesaving valid data in another memory block. This can make data renewaland erasure faster.

Physical addresses may be allocated to the logical pages in which casethe memory device may comprise, for example, a memory (123) for storingan address translation table representing a correlation between thephysical addresses of the logical pages and logical addresses to be usedto specify the logical pages by an external unit, and a memory (123) forstoring a write pointer that points the empty logical page in thelogical pages which is in a data storable state and instructs thephysical address of the specified empty logical page, and

when to-be-written data and a logical address are supplied to the memorydevice, the controller (12) may write the to-be-written data in theempty logical page pointed by the write pointer, and renew the addresstranslation table in such a way as to show a correlation between thephysical address of the empty logical page and the logical address(S321).

This structure eliminates the need for an operation of searching for anew empty block (a block where user data is not stored) and writing dataevery time data writing takes place. Even in case where erasure of olddata accompanies data writing (specifically, in case of performing datarewriting), inefficient flash erase need not be performed on memoryblocks, thus suppressing the degrading of the memory device.

The controller (12) may write validity data indicating that the writtento-be-written data is valid in the physical page which includes thelogical page where the to-be-written data is stored (S314). In thiscase, the logical page where data is not stored may be specified basedon the validity data and the specified logical page may be treated asthe empty logical page.

The area where the validity data is to be written is an area which isnot included in any one of logical pages in that physical page whichincludes the logical page that stores the to-be-read page.

The controller (12) may discriminate whether or not data stored in eachof the logical pages in to-be-erased memory blocks is valid based on thevalidity data (S501), specify that logical pages which are located inanother memory blocks and where data is not stored and transfer thatdata which has been discriminated as valid into the specified logicalpages (S502 and S503, S507), and erase data stored in the to-be-erasedmemory blocks (S504).

When information for specifying a to-be-read logical page to be read outis supplied to the memory device, the controller (12) may specify theto-be-read logical page based on the information, read data from thespecified to-be-read logical page and send the read data outside (S201to S214).

According to the second aspect of the invention, there is provided amemory managing method of managing a memory (11) including a pluralityof memory blocks which stores data and each of which is comprised of oneor more physical pages each including one or more logical pages,characterized by comprising the steps of:

writing, when to-be-written data is supplied to the memory, theto-be-written data in that empty logical page in the logical pages whichis in a data storable state (S314); and

discriminating whether to-be-replaced data to be replaced with theto-be-written data is stored in the logical pages, and writing validitydata indicating that the to-be-replaced data is not valid in thatphysical page which includes the logical page that stores theto-be-replaced data, when it is discriminated that the to-be-replaceddata is stored in the logical page (S308 to S310).

According to the memory managing method, to-be-replaced data (old databefore renewal in case of renewing data) is indicated as invalid by thevalidity data instead of being erased. Therefore, inefficient flasherase need not be performed on memory blocks at the time of renewal,thus suppressing the degrading of the memory device.

Further, the location of invalid data is specified by referring to thevalidity data. Even if reading of data in a logical page indicated bythe validity data is omitted in case of erasing the memory contents of amemory block, it is possible to properly erase the invalid data whilesaving valid data in another memory block. This can make data renewaland erasure faster.

According to the third aspect of the invention, there is provided aprogram for allowing a computer (121), connected to a memory (11)including a plurality of memory blocks which stores data and each ofwhich is comprised of one or more physical pages each including one ormore logical pages, to function to:

write, when to-be-written data is supplied to the memory, theto-be-written data in that empty logical page in the logical pages whichis in a data storable state (S314); and

discriminate whether to-be-replaced data to be replaced with theto-be-written data is stored in the logical pages, and write validitydata indicating that the to-be-replaced data is not valid in thatphysical page which includes the logical page that stores theto-be-replaced data, when it is discriminated that the to-be-replaceddata is stored in the logical page (S308 to S310).

With the use of a computer which executes this program, to-be-replaceddata (old data before renewal in case of renewing data) is indicated asinvalid by the validity data instead of being erased. Therefore,inefficient flash erase need not be performed on memory blocks at thetime of renewal, thus suppressing the degrading of the memory device.

Further, the location of invalid data is specified by referring to thevalidity data.

Even if reading of data in a logical page indicated by the validity datais omitted in case of erasing the memory contents of a memory block, itis possible to properly erase the invalid data while saving valid datain another memory block. This can make data renewal and erasure faster.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating the structure of a memory systemaccording to one embodiment of the invention.

FIG. 2 is a diagram exemplarily showing the logical structure of thememory area of a flash memory.

FIG. 3 is a diagram exemplarily showing the data structures of adirectory and FAT.

FIG. 4 is a diagram exemplarily showing the data structure of a BSI(Block Search Index).

FIG. 5 is a diagram exemplarily showing the data structure of a BPT(Block Pointer Table).

FIG. 6 is a flowchart illustrating an initialization process.

FIG. 7 is a flowchart illustrating a data reading process.

FIG. 8 is a flowchart illustrating a data writing process.

FIG. 9 is a flowchart illustrating a directory and FAT renewal process.

FIG. 10 is a flowchart illustrating an empty block securing process.

FIG. 11 is a block diagram illustrating the structure of a modificationof the memory system in FIG. 1.

BEST MODE FOR CARRYING OUT THE INVENTION

One embodiment of the invention will be described below, taking a memorysystem equipped with a flash memory as an example, with reference to theaccompanying drawings.

FIG. 1 is a block diagram illustrating the physical structure of thememory system according to the embodiment of the invention.

As illustrated, the memory system comprises a memory unit 1 and acomputer 2. The memory unit 1 is attached in a detachable manner to thecomputer 2 via a slot provided in the computer 2.

The slot of the computer 2 comprises, for example, a PCMCIA slot forrelaying a PCMCIA bus.

The memory unit 1 comprises a flash memory 11 and a controller 12.

The flash memory 11 is comprised of a memory device, such as EEPROM(Electrically Erasable/Programmable Read Only Memory).

In response to an access made by the controller 12, the flash memory 11stores data supplied from the computer 2, supplies stored data to thecomputer 2 and erases stored data.

The memory area the flash memory 11 has consists of, for example, 65,536physical pages as shown in FIG. 2, each physical page having a memorycapacity of 2,112 bytes.

Each physical page is comprised of four logical pages each consisting of512 bytes and a redundancy portion which occupies the last 64 bytes ofthe physical page. Memory cells included in each logical page are givenconsecutive addresses from “0” to “511”.

As illustrated, each logical page consists of a data area which occupiesan area of 512 bytes from the top and a redundancy portion whichoccupies an end area of 64 bytes.

User data (data supplied from the computer 2 and written or data to besupplied to the computer 2) is stored in a logical page.

An ECC (Error-Correcting Code) for checking if the contents of user datastored in each logical page which belongs to the same physical page asthe redundancy portion does are not corrupted and a defective block flagare stored in the redundancy portion.

The defective block flag is data indicating whether a block (to bediscussed later) to which a physical page where the defective block flagis stored belongs is a block capable of properly storing data (goodblock), a block which is not a good block, i.e., a defective block andhas been decided as defective before shipment by the manufacturer or thelike of the flash memory 11 (initially defective block), or a blockwhich is a defective block and is decided as being unable to properlystore data during the use of the flash memory 11 (later-generateddefective block).

It is to be noted that the defective block flag that shows a good blockcan be updated so as to be able to indicate a later-generated defectiveblock when it is overwritten with a value indicating a later-generateddefective block.

A NAND type flash memory can overwrite a value “0” in a memory cellstoring a value “1”. (This type of flash memory cannot overwrite a value“1” in a memory cell storing a value “0” and a block including thismemory cell should be flash-erased (to be discussed later) once.)

Suppose therefore that the flash memory 11 is a NAND type flash memoryand the defective block flag consists of data of two bits. In this case,provided that a value indicating a good block is “11”, a valueindicating a later-generated defective block is “01” or “10” and a valueindicating an initially defective block is “00”, the defective blockflag can be updated to show a later-generated defective block as it isoverwritten with the value that indicates a later-generated defectiveblock. This manipulation eliminates the need for flash-erasing a blockwhich has the defective block flag.

A valid flag which indicates how many of the individual logical pagesbelonging to the same physical page where the redundancy portion islocated stores invalid user data is stored in the redundancy portionthrough a process to be discussed later. The cases where user datastored in a logical page is invalid include, for example, a case whereupdated data of the data is stored in another logical page in the flashmemory 11.

It is to be noted that the valid flag indicating that one logical has noinvalid data stored therein can be updated to show that this logicalpage is having invalid data if the flag is overwritten.

Every 64 physical pages starting from the top constitute a single block.Each block has 256 logical pages to which consecutive page addressesfrom “0” to “255” are allocated. The entire memory area of the flashmemory 11 comprises 1,024 blocks which are given consecutive physicalblock addresses of “0” to “1023”.

The value of a logical address which is allocated to each logical pagein each physical page is stored in the redundancy portion of thatphysical page. The logical address is a unit which is recognized as adata reading/writing unit by the controller 12 when the flash memory 11is read or written through an operation to be discussed later.

The logical address of a logical page consists of, for example, upperdigits (logical block address) indicating a block to which the logicalpage belongs and lower digits (page address) indicating the location ofthe logical page in the block. The total number of logical addresses isa predetermined value, for example, 256,000, smaller than the totalnumber of logical pages the flash memory 11 physically has (there are1,024 blocks each containing 256 logical pages, which amounts to thetotal number of 262,144 logical pages).

When the flash memory 11 is instructed to erase data in a specific blockby the controller 12 of the memory unit 1, it flash-erases the memorycontents of all the memory cells that are included in the block.(Specifically, in case where the flash memory 11 is of a NAND type, thememory value of each memory cell is set to “1”.)

A directory, FAT (File Allocation Table) and write pointer initial valueare stored in the logical page of the flash memory 11, and are renewedby a process to be discussed later.

The logical page where the directory, FAT and write pointer initialvalue are stored is given a logical address which meets a predeterminedcondition. Specifically, for example, the top 4,096 addresses (i.e.,addresses 0h to FFFh) are given as a logical address. (Throughout thespecification and in the drawings, a numeral with a letter “h” affixedto the end represents a hexadecimal numeral.)

FIG. 3 is a diagram showing the correlation among the directory, FAT andlogical block address. As illustrated, the logical address of thelogical page where the directory, FAT and write pointer initial valueare stored is pointed by, for example, a directory pointer stored in aCPU (Central Processing Unit) 121 (or stored in a RAM (Random AccessMemory) 123 by the CPU 121).

The directory is a table showing the names of files stored in the flashmemory 11 (i.e., a collection of data designated by the computer 2 as acollective target to be handled) and logical addresses of logical pageswhere the head portions of the files are stored.

The FAT is a table indicating the layout of files in the memory area inthe flash memory 11 and indicates the logical address of a logical pagewhich stores a subsequent part as shown in FIG. 3 when a file does notfit in one logical page. The logical address of the logical page wherethe last part of a file is stored is given an end code (EC) as shown inFIG. 3 to indicate that the logical page address represents the lastpart.

The write pointer initial value represents the latest value of a writepointer (to be discussed later) which is a variable indicating a logicalpage where the CPU 121 should write user data, and designates thelogical page where user data should be written at the time the memorysystem writes the user data in the flash memory 11 for the first timeafter having been activated.

The controller 12 has the CPU 121, a ROM (Read Only Memory) 122 and theRAM 123, as shown in FIG. 1. The RAM 123 is comprised of, for example,SRAM (Static RAM).

The CPU 121 is connected to the ROM 122, RAM 123 and flash memory 11 andis connected to the computer 2 via the PCMCIA slot provided in thecomputer 2.

The CPU 121 performs processes to be discussed later in accordance withprocesses executed by a program prestored in the ROM 122 by themanufacturer or the like of the controller 12.

When acquiring a command supplied from the computer 2 which constitutesan access device, the CPU 121 executes the command. Commands the CPU 121executes include a command to access the flash memory 11.

The memory area the RAM 123 has is used as a work area for the CPU 121and includes a saving memory area. The memory area further stores a BSI(Block Search Index) and BPT (Block Pointer Table) which are generatedby the CPU 121 in processes to be discussed later and a write pointer.

The saving memory area is a memory area to temporarily store data storedin a block which includes a logical page to be subjected to writing in adata writing process to be discussed later.

The BSI stores information that specifies which one of the individualblocks included in the memory area of the flash memory 11 is an emptyblock (i.e., a block which has been flash-erased and is no long storinguser data). The BSI is generated and renewed (by the controller 12)according to processes of the controller 12 to be discussed later.

FIG. 4 shows one example of the structure of the BSI when the totalnumber of blocks in the flash memory 11 is 1,024. As illustrated, theBSI consists of data of one Kbytes, with their bits being associated,one to one, with the first block to the 1024-th block in order from thetop bit. The BSI stores “1” when the associated block is an empty blockand “0” when the block is not an empty block.

The BPT stores information on each logical page showing the correlationbetween the logical address and physical address of that logical page.The BPT is generated or renewed according to a process (to be discussedlater) which is executed by the CPU 121.

Specifically, the BPT has a data structure as shown in FIG. 5, forexample.

The BPT has a memory area which occupies a predetermined position in thememory area in, for example, the RAM 123 and stores physical addressesassociated with the respective logical addresses. Given that there are256,000 logical addresses in total, as illustrated, the memory area ofthe BPT should have a size of a total of 576,000 bytes with addresses 0hto 3E7FFh each given every 18 bits starting from the top.

In case where the BPT has the data structure shown in FIG. 5, each ofthe addresses allocated to the memory area that forms the BPT is equalto the sum of the logical address and a predetermined offset value.

The content of each 18-bit memory area to which an associated address isallocated represents the physical address (a set of a physical blockaddress and a page address) of a logical page associated with thelogical address indicated by the address of the 18-bit memory area.

Suppose that, as shown in FIG. 5, a value “0A10Fh” is stored in thememory area to which the address 0001h is allocated and the offset valueis “0000h”. In this case, a logical address “0001h” is associated withthe logical page whose physical address is “0A10Fh” (the physical blockaddress is “0A1h” and the page address is “0Fh”).

In case where the content stored in a memory area allocated with anassociated address represents a predetermined value (e.g., in case wherethe content represents the physical address value of “3FFFFh” asillustrated), no physical address is associated with the logical addressindicated by the address of the memory area where the value is stored.

The write pointer is a variable (pointer) which points a logical pagewhere the CPU 121 should write user data and specifically indicates thephysical address of the associated logical page. The value of the writepointer is updated according to a process to be discussed later.

The computer 2 is comprised of a personal computer or the like, has thePCMCIA slot, has an OS and program data, representing drivers, storedtherein, and executes the OS after being powered on. When the computer 2detects the installment of the memory unit 1 in the PCMCIA slot, itactivates the drivers according to the processes of the OS.

The computer 2 which executes the processes of the drivers supplies thecontroller 12 with the aforementioned commands or supplies the flashmemory 11 with data to be written and allows the CPU 121 to access theflash memory 11. The computer 2 acquires, from the CPU 121, data whichhas been read from the flash memory 11 and supplied to the computer 2 bythe CPU 121 in response to the command sent from the computer 2.

(Operation)

The operation of this memory system will be described below referring toFIGS. 6 to 10.

FIG. 6 is a flowchart illustrating an initialization process. FIG. 7 isa flowchart illustrating a data reading process. FIG. 8 is a flowchartillustrating a data writing process. FIG. 9 is a flowchart illustratinga directory and FAT renewal process. FIG. 10 is a flowchart illustratingan empty block securing process.

Initialization Process

As the memory system is activated, the CPU 121 of the controller 12 inthe memory unit 1 executes the initialization process shown in FIG. 6.

As the initialization process starts, the CPU 121 initializes thoseportions in the memory area in the RAM 123 where the BPT and BSI arestored (step S101 in FIG. 6).

In step S101, specifically, the CPU 121 writes a predetermined value(e.g., the aforementioned value “3FFFFh”), which indicates that aphysical address is not associated with each 18-bit area indicated bythe aforementioned address, in that portion in the memory area in theRAM 123 where the BPT is stored. The CPU 121 sets the values of all thebits of the portion where the BSI is stored to “0”.

Next, the CPU 121 specifies a block with the youngest physical blockaddress from among those blocks from whose redundancy portions data hasnot been read out yet and reads every data stored in the redundancyportions of the individual physical pages which belong to the specifiedblock (step S102).

Then, based on the data read in step S102, the CPU 121 discriminateswhether the block from which data has been read out in step S102 is anempty block or not (step S103). Specifically, for example, the CPU 121discriminates whether the data read out in step S102 is an empty blockcode (e.g., the aforementioned “3FFFFh”) of a predetermined format ornot. When the CPU 121 discriminates that the read block is not an emptyblock, the CPU 121 moves the process to step S105.

When the CPU 121 discriminates in step S103 that the read block is anempty block, the CPU 121 computes, from the physical block addressindicating the block, the position in the memory area of the RAM 123where the bit in the BSI which indicates the status of the blockoccupies. Then, the CPU 121 rewrites the value of the position-computedbit with “1” (step S104). When the process of step S104 is done, the CPU121 moves the process to step S106.

Meantime, in step S105, the CPU 121 writes the physical address of eachlogical page whose logical address has been read out from the redundancyportion of the flash memory 11 in the memory area of the RAM 123. Thelogical position (in the RAM 123) where the CPU 121 writes the physicaladdress of the logical page in step S105 is the portion to which anaddress equivalent to the logical address read from that logical page,read from the redundancy portion, is given. Accordingly, new informationindicating the correlation between the physical address and the logicaladdress is added to the BPT.

When completing the process of step S105 for all the logical addressesread from the same block in the flash memory 11, the CPU 121 moves theprocess to step S106.

In step S106, the CPU 121 discriminates whether or not there is a nextblock to the block from whose redundancy portion data has been read outin step S102. The CPU 121 returns the process to step S102 when havingdiscriminated that there is a next block, but moves the process to stepS107 when having discriminated that there is no next block.

In step S107, the CPU 121 accesses a logical page where the writepointer initial value is stored, reads the write pointer initial valueand stores the value in the RAM 123, after which the CPU 121 terminatesthe initialization process.

Through the above-described initialization process, the BSI and BPT aregenerated and the write pointer initial value is specified.

(Data Reading Process)

As the initialization process is completed, the CPU 121 in the memoryunit 1 accepts a read instruction to access the flash memory 11 from thecomputer 2.

To instruct the CPU 121 to read data from the flash memory 11, thecomputer 2 first supplies the CPU 121 with a read command to read adirectory and FAT and the logical address of each logical page where thedirectory and FAT are stored (step S201 in FIG. 7).

The CPU 121, supplied with the command to read data and the logicaladdress, searches the BPT for the physical address of each logical pagewhere the directory and FAT are stored with the logical address as akey, reads data constituting the directory and FAT from each logicalpage indicated by the searched physical address and supplies the data tothe computer 2 (step S202). The computer 2 temporarily stores thedirectory and FAT supplied from the CPU 121.

Next, to search for the logical address of the top logical page wherethe file content which has the file name of a file containing to-be-readdata is stored, the computer 2 searches the directory, supplied from theCPU 121 and temporarily stored, with the file name as a key (step S203).

Next, with the logical address searched in step S203 as a key, thecomputer 2 searches the FAT supplied from the CPU 121 to retrieve alllogical addresses of logical pages, if present, which follow the pagewhose logical address has been retrieved, and specifies the consecutiveorder of the logical pages (step S204).

Then, to read the memory contents of the logical pages retrieved insteps S203 and S204, the computer 2 supplies the CPU 121 with a readcommand and the logical address of that logical page from which userdata should be read out (i.e., the top one of the logical pages whichhave been retrieved in steps S203 and S204 and from which data has notbeen read out yet) (step S205).

When supplied with the read command and the logical address in stepS205, the CPU 121 accesses the RAM 123 and searches the BPT with thelogical address supplied from the computer 2 in step S205 as a key todiscriminate whether or not there is a physical address associated withthe logical address (step S206).

When having discriminated that there is no such a physical address, theCPU 121 supplies an error message (e.g., a predetermined “FFh”) to thecomputer 2 (step S207) and terminates the data reading process (abort).

When having discriminated that there is such a physical address, the CPU121 reads data from the logical page indicted by the physical addressand reads the ECC of that logical page from the redundancy portion ofthe same physical page to which the logical page belongs (step S208).

Then, the CPU 121 generates an ECC based on that data in the data readin step S208 which is stored in the logical page and discriminateswhether or not the data stored in the logical page has been read outcorrectly, based on the generated ECC and an ECC in the read data whichhas been stored in the redundancy portion (step S209).

When having discriminated in step S209 that the data was read outcorrectly, the CPU 121 supplies data stored in the logical page to thecomputer 2 (step S210).

When having discriminated that the data was not read out correctly, theCPU 121 discriminates whether or not the data stored in the logical pagecan be corrected to the correct content based on the ECC or the likestored in the redundancy portion (step S211). When having discriminatedthat data restoration would be possible, the CPU 121 corrects the datastored in the logical page and supplies the corrected data to thecomputer 2 (step S212).

When having discriminated in step S211 that correction would not bepossible, the CPU 121 overwrites the defective block flag stored in theredundancy portion of the same physical page to which the logical pagefrom which the uncorrectable data has been read belongs (or theredundancy portion of another arbitrary physical page in the same blockto which the former logical page belongs) with a value representing alater-generated defective block and notifies the computer 2 of failureof data reading (step S213). Upon reception of the notification, thecomputer 2 interrupts the data reading process (abort).

When the computer 2 receives to-be-read data from the CPU 121 in stepS210 or S212, the computer 2 discriminates whether or not there is anylogical page remaining from which user data should be read out (stepS214). Then, the computer 2 returns the process to step S205 when havingdiscriminated that there is such a logical page remaining, andterminates the process when having discriminated that there remains nosuch a logical page.

Through the above-described processes of steps S201 to S214, data isread from the flash memory 11 and supplied to the computer 2.

(Data Writing Process)

In case of writing data in the flash memory 11, first, to read adirectory and FAT, the computer 2 first supplies the CPU 121 with a readcommand and the logical address of each logical page where the directoryand FAT are stored as done in the step S201 (step S301 in FIG. 8). It isto be noted however that in case where the directory and FAT havetemporarily been stored already for some purpose, such as reading data,the process of step S301 is omitted and the data writing process startsat step S303.

The CPU 121, supplied with the command to read data and the logicaladdress, performs substantially the same process as that of the stepS202 to read the directory and FAT and supplies them to the computer 2(step S302). The computer 2 temporarily stores the directory and FATsupplied from the CPU 121.

Next, with the file name of the file to be written in the flash memory11 as a key, the computer 2 searches the directory supplied from the CPU121 and discriminates whether or not the file name is stored in thedirectory (step S303). When the decision is negative, the computer 2moves the process to step S305 to be discussed later.

When the decision in step S303 is affirmative, on the other hand, thecomputer 2 searches the FAT supplied from the CPU 121 using the logicaladdress, associated with the file name retrieved in the searching instep S303, as a key. Then, the computer 2 retrieves the logical addressof each logical page which holds data indicated by the file name andtemporarily stores the logical address (step S304), and moves theprocess to step S305.

In step S305, the computer 2 decides data to be supplied to the CPU 121in steps S306 and S313 to be discussed later.

Specifically, in step S305, the computer 2 first discriminates whetheror not writing of the to-be-written file has been completed. When thedecision is negative, the computer 2 decides to supply one logical pageof data which is included in data contained in the to-be-written fileand which has not been written in the flash memory 11 yet in step S313and decide to supply the logical address (the logical address of thewrite destination) of the logical page that holds this data in stepS306.

When having discriminated that writing of the to-be-written file hasbeen completed, on the other hand, the computer 2 discriminates whetheror not the directory and FAT, temporarily stored therein, have beenwritten in the flash memory 11. When having discriminated that thewriting has not been finished, the computer 2 decides to supply onelogical page of data constituting the directory and FAT, temporarilystored in the computer 2, in step S313 and decide the logical address(the logical address of the write destination) of the logical page wherethe directory and FAT should be stored.

When the computer 2 has discriminated that writing of the directory andFAT has been completed too, the computer 2 decides to supplypredetermined data to notify the completion of the writing in step S306.

In step S306, the computer 2 supplies the logical address of theto-be-written logical page to store data or notification of thecompletion of writing in accordance with the result of the decision madein step S305. In case of supplying the logical address, the computer 2also supplies a command to write one logical page of data in the flashmemory 11.

In case where the computer 2 has decided to supply data contained in theto-be-written file in step S313, the computer 2 executes the directoryand FAT renewal process shown in FIG. 9 to decide the logical address tobe supplied to the CPU 121 in step S306 and renewal of the directory andFAT.

That is, the computer 2 first analyzes the directory and FAT temporarilystored therein and specifies logical addresses of logical pages wheredata is not written (i.e., the logical addresses which are notassociated with the file name) by the quantity required for storingto-be-written data as logical addresses that should be allocated to theto-be-written logical pages (step S401 in FIG. 9).

When having discriminated in step S303 that the file name of theto-be-written file is included in the directory, the computer 2 mayspecify the logical address associated with this file name (i.e., thelogical address temporarily stored in step S304) by priority as thelogical address of the logical page where data is to be written.

Next, the computer 2 decides the aligning order of the individuallogical addresses specified in step S401 (step S402). This aligningorder represents the aligning order of the individual logical pages towhich those logical addresses are allocated and represents the aligningorder of data written in those logical pages.

When the computer 2 has carried out the processes of steps S401 andS402, the controller 12 has only to supply the CPU 121 with the logicaladdress which is included in those logical addresses specified in stepS401 and not having supplied to the CPU 121 yet and which corresponds tothe top in the aligning order decided in step S402.

Next, the computer 2 stores the logical address specified in step S401in the directory and FAT, temporarily stored in the computer 2, in sucha way as to take the data structure shown in FIG. 3 (step S403). Therelationship between addresses precedent and subsequent to the logicaladdress represented by the directory and FAT should match the orderspecified in step S401. The process of step S403 generates a directoryand FAT to be newly written in the flash memory 11.

When the CPU 121 is supplied with data, such as the logical address ofthe write destination or notification of completion of writing, from thecomputer 2 in step S306, the CPU 121 discriminates whether or notnotification of completion of writing is included in those data (stepS307 in FIG. 8). The CPU 121 moves the process to step S319 when thedecision is affirmative and carries out processes starting at step S308when the decision is negative.

In step S308, the CPU 121 accesses the RAM 123 and searches the BPT forthe physical address of the logical page that is indicated by thelogical address supplied from the computer 2. Then, the CPU 121discriminates whether or not the physical address has been retrieved instep S308 (step S309) and moves the process to step S311 when thedecision is negative.

When having discriminated in step S309 that the physical address hasbeen retrieved, the CPU 121 accesses the flash memory 11, updates thevalid flag in the redundancy portion of the physical page to which thelogical pages having the retrieved physical address allocated thereto insuch a way as to indicate that those logical pages have invalid datastored therein (step S310), and moves the process to step S311. In stepS310, the CPU 121 accesses the RAM 123 and renews the physical addressspecified in step S308 to a value indicating that the physical addresshas not been associated yet (e.g., the aforementioned value “3FFFFh”).That is, the allocation of the logical address to this logical page isrelieved.

In step S311, the CPU 121 accesses the RAM 123 and stores the physicaladdress currently pointed by the write pointer in the BPT in such a formas to be associated with the logical address of the write destinationsupplied from the computer 2. Then, the CPU 121 stands by for the supplyof one logical page of data to be written in the flash memory 11 fromthe computer 2 (step S312).

When data to be written in the flash memory 11 is supplied from thecomputer 2 (step S313), the CPU 121 accesses the flash memory 11 andwrites one logical page of data supplied from the computer 2 in thelogical page that is currently pointed by the write pointer (step S314).In step S314, the CPU 121 writes, as the logical address of this logicalpage, the logical address supplied from the computer 2 in step S306 inthe redundancy portion of the same physical page to which that logicalpage belongs.

Next, the CPU 121 accesses the RAM 123 and discriminates whether or notthe page in which data has been newly written in step S314 is the endpage of the block containing this page, based on, for example, thecurrent value of the write pointer (step S315). When havingdiscriminated that the page in question is not the end page, the CPU 121moves the process to step S318.

When having discriminated in step S315 that the page where data has beennewly written is the end page of the block, on the other hand, the CPU121 renews the content of the BSI stored in the RAM 123 in such a way asto indicate that this block is not an empty block (step S316).

Next, the CPU 121 determines whether or not the block should beflash-erased to secure an empty block based on an arbitrary reference(step S317). For example, the CPU 121 has only to count the number ofcurrent empty blocks based on the content of the BSI, decide that anempty block should be secured when the number of empty blocks is equalto or smaller than two and decide that an empty block need not besecured when the number of empty blocks is equal to or greater thanthree.

The CPU 121 moves the process to step S318 when having decided that anempty block need not be secured, but initiates the empty block securingprocess shown in FIG. 10 when having decided that an empty block shouldbe secured.

As the empty block securing process starts, the CPU 121 specifies one ormore blocks from which data is to be flash-erased to turn them to emptyblocks (step S501 in FIG. 10).

The reference for determining a block to be flash-erased by the CPU 121in step S501 is set arbitrarily; for example, the CPU 121 has only todetermine, as a target to be flash-erased, a non-empty block (a blockother than an empty block) which is included in those blocks subsequentto the latest block that has been flash-erased to become an empty block(i.e., blocks that are given physical block addresses larger than thephysical block address of the latest block) and which has the smallestphysical block address. In case where there is no such a non-emptyblock, however, that one of all the non-empty blocks in the flash memory11 which has the smallest physical block address is to be flash-erased.

Next, the CPU 121 specifies every logical page in the individual logicalpages in the block specified in step S501 which holds valid user data byreferring to the valid flag stored in the redundancy portion of eachphysical page in the specified block (step S502). Then, the CPU 121reads user data (to-be-saved data) from each logical page specified instep S502 and stores the data in the RAM 123 (step S503). In step S503,the CPU 121 also reads the logical address of each logical pagespecified in step S502 and the ECC of the to-be-saved data from theredundancy portion and stores them in the RAM 123.

Next, the CPU 121 flash-erases the block specified in step S501 to turnit to an empty block and writes an empty block code in the redundancyportion of each physical page in the block that has just become an emptyblock (step S504). (It is to be noted however that in case where theflash memory 11 is of a NAND type and the empty block code consists onlyof bits which have values of “1, it is not particularly necessary toexecute the operation of writing the empty block code.)

The CPU 121 accesses the RAM 123 and renews the content of the BSI insuch a way as to indicate that this block is an empty block (step S505).

Next, the CPU 121 increments the write pointer (step S506).Specifically, by referring to the redundancy portion of the physicalpage that contains those logical pages which follow the logical pagecurrently pointed by the write pointer, the CPU 121 specifies the topone of those logical pages which follow the logical page currentlypointed by the write pointer and have no logical addresses written inthe redundancy portion. Then, the CPU 121 renews the value of the writepointer stored in the RAM 123 in such a way as to point the physicaladdress of the specified logical page. In case where the logical pagecurrently pointed by the write pointer is the end logical page of theblock, however, the CPU 121 should search the BSI to specific a newsingle empty block, specify the top logical page of the specified emptyblock and renew the value of the write pointer stored in the RAM 123 insuch a way as to point the physical address of the specified top logicalpage in step S506.

Next, the CPU 121 writes new to-be-saved data back (step S507). That is,of those pieces of to-be-saved data stored in the RAM 123 in step S503,one logical page of data which has not been written back into the flashmemory 11 is written in the logical page that is currently pointed bythe write pointer. The CPU 121 may erase that portion of the to-be-saveddata which has been written back into the flash memory 11 from thememory area of the RAM 123.

In step S507, the CPU 121 writes the logical address allocated to thelogical page where new to-be-saved data which should be written back hasbeen stored before, in the redundancy portion of the physical page whichcontains the logical page currently pointed by the write pointer as thelogical address of that logical page.

Next, the CPU 121 accesses the RAM 123 stores the physical addresscurrently 10 pointed by the write pointer (i.e., the physical address ofthe logical page where to-be-saved data has newly been written) in theBPT in association with the logical address of the logical page whereto-be-saved data has newly been written in step S507 (step S508).

Next, the CPU 121 discriminates whether or not every to-be-saved datahas been written back (step S509) and returns the process to step S506when having discriminated that some to-be-saved data has not beenwritten back.

When having discriminated in step S509 that every to-be-saved data hasbeen written back, the CPU 121 terminates the empty block securingprocess and increments the write pointer in the same way as done in theprocess of step S506 (step S318) and stands by for the supply of thelogical address of the next write destination or notification ofcompletion of writing from the computer 2.

As the CPU 121 goes to the mode to sand by for the supply of the logicaladdress of the next write destination or notification of completion ofwriting from the computer 2, the computer 2 returns the process to stepS305. Then, when the logical address of the next write destination ornotification of completion of writing from the computer 2 is suppliedfrom the computer 2 in step S306, the CPU 121 returns the process tostep S307.

As the CPU 121 moves the process to step S319 upon reception of thenotification of completion of writing, the CPU 121 performs a processsimilar to the process of step S506 to acquire the result ofincrementing the current value of the write pointer stored in the RAM123 and temporarily stores the result. It is to be noted that the writepointer does not increment itself.

Next, the CPU 121 stores the physical address currently pointed by thewrite pointer in the BPT in such a form as to be associated with thephysical address (the logical address for the pointer initial value)that is allocated to the logical page where the write pointer initialvalue is stored (step S320).

Next, the CPU 121 writes the value obtained in step S319 as the writepointer initial value in the data area of the page currently pointed bythe write pointer (step S321). In step S321, the logical address for thepointer initial value is written in the redundancy portion of the samephysical page to which this logical page belongs, as the logical addressof the logical page.

When the process of step S321 is finished, the memory system terminatesthe data writing process.

Through the above-described processes, data supplied from the computer 2is stored in the flash memory 11. The content of the BSI is changed insuch a way as to indicate an empty block which has been newly generatedas a result of writing data and indicate a vanished empty block.Meantime, the content of the BPT is also changed and the logical addressthat has been allocated to a logical page having stored valid user datain that block which has newly become an empty block is newly allocatedto that logical page whose content has been transferred.

In this memory system, in case where user data is to be renewed, olduser data is specified as invalid by the valid flag instead of beingerased. Therefore, the memory system does not require inefficient flasherase of blocks at the time of renewal, thus making the degrading of theflash memory 11 harder to occur.

In case where valid user data is to be transferred in order to secure anempty block, the process proceeds without involving reading of data fromthe logical page that is specified as invalid by the valid flag. Thiscan allow an empty block to be secured faster.

The structure of the memory system is not limited to the one describedabove.

For example, the number of blocks in the memory area of the flash memory11, the number of logical pages per block, the memory capacity of eachlogical page and the memory capacities of the logical page andredundancy portion are all arbitrary. Further, the flash memory 11should not necessarily be constituted by an EEPROM but may be any memorydevice readable and writable by a computer.

The logical addresses of logical pages where the directory and FAT arestored need not take the aforementioned value, and the number of logicalpages where the directory and FAT are stored is arbitrary.

The redundancy portion in the flash memory 11 should not necessarily belocated at the end of each physical page but may be provided at anylocation in the physical page or the location of the redundancy portionmay be allocated dynamically.

The RAM 123 may be a non-volatile memory constituted by, for example,FeRAM (Ferroelectric RAM). In this case, the memory system may notrequire the initialization process if the BSI and BPT have already beenstored in the RAM 123. That is, the BPT and BSI should not necessarilybe generated every time the memory system is activated.

The CPU 121 should not necessarily be connected to the computer 2 viathe PCMCIA slot but may be connected to the computer 2 via an IEEE 1394interface or USB (Universal Serial Bus) or any other interface. The CPU121 should not necessarily be connected to the computer 2 by a cable butmay wirelessly be connected to the computer 2 via an interface whichconforms to the standards, such as Bluetooth (registered trademark).

The flash memory 11 should not necessarily be fixed inside the memoryunit 1, but may be connected to, for example, the controller 12 in adetachable manner. In this case, the flash memory 11 and the controller12 should be constructed in such a way as to be connected together via,for example, terminals similar to the terminals of a smart medium(registered trademark) and its drive unit, or terminals similar to theterminals of a compact flash (registered trademark) and its drive unit.

The installed memory unit 1 and the computer 2 may be connected to eachother in a fixed manner or the memory unit 1 and the computer 2 may beassembled in the same casing as shown in FIG. 11.

While the embodiment of the invention has been described above, thememory system of the invention is not limited to an application-specificsystem but may be realized by using an ordinary computer system. Forexample, a memory system which executes the above-described processescan be constructed by installing a program for executing theabove-described processes into a personal computer having a slot tomount the flash memory 11 from a medium (flexible disk, CD-ROM or thelike) having the program stored therein.

The program may be uploaded to, for example, a BBS via a communicationcircuit and distributed via the communication circuit. Alternatively, acarrier wave may be modulated with a signal representing the program,the obtained modulated wave may be transmitted and a device whichreceives the modulated wave may demodulate the modulated wave to restorethe program.

Then, the above-described processes can be executed by activating theprogram and executing the program in the same manner as otherapplication programs under the control of the OS.

In case where the OS performs some of the processes, or the OSconstitutes a part of a single structural element of the invention, theprogram excluding that portion may be stored in the recording medium. Itis premised in this case too that a program for performing theindividual functions or steps which are executed by a computer is storedin the recording medium in the invention.

The invention is based on Japanese Patent Application No. 2002-179902filed on Jun. 20, 2002, and includes the specification, claims, drawingsand abstract of that application. The present specification incorporateswhat is disclosed in the application entirely by reference.

INDUSTRIAL APPLICABILITY

The invention can be adapted to a memory device which is readable andprogrammable by a computer.

1. A memory device characterized by comprising: a non-volatile memoryincluding a plurality of memory blocks which stores data and each ofwhich is comprised of one or more physical pages each including one ormore logical pages and a redundancy portion; and a controller which,when to-be-written data is supplied to said memory device, writes saidto-be-written data in that empty logical page in said logical pageswhich is in a data storable state, discriminates whether to-be-replaceddata to be replaced with said to-be-written data is stored in saidlogical pages, and writes validity data indicating that saidto-be-replaced data is not valid in that physical page which includessaid logical page that stores said to-be-replaced data, when havingdiscriminated that said to-be-replaced data is stored in said logicalpage.
 2. The memory device according to claim 1, characterized in thatwhen information for specifying a to-be-read logical page to be read outis supplied to said memory device, said controller specifies saidto-be-read logical page based on said information, reads data from saidspecified to-be-read logical page and sends said read data outside. 3.The memory device according to claim 1, characterized in that physicaladdresses are allocated to said logical pages, said memory devicefurther comprises a second memory which is randomly accessible andstores an address translation table representing a correlation betweensaid physical addresses of said logical pages and logical addresses tobe used to specify said logical pages by an external unit, and a thirdmemory which is randomly accessible and stores a write pointer thatpoints the empty logical page in said logical pages which is in a datastorable state and instructs the physical address of said specifiedempty logical page, when this memory device is activated, saidcontroller reads the redundancy portions of said non-volatile memory andprepares the address translation table in said second memory and thewrite pointer in said third memory; and when to-be-written data and alogical address are supplied to said memory device, said controllerwrites said to-be-written data in said empty logical page pointed bysaid write pointer, and renews said address translation table in such away as to show a correlation between said physical address of said emptylogical page and said logical address.
 4. The memory device according toclaim 1, characterized in that said controller writes said validity datain an area which is not included in any one of logical pages in thatphysical page which includes said logical page that stores saidto-be-replaced data.
 5. The memory device according to claim 3,characterized in that said controller writes validity data indicatingthat said written to-be-written data is valid in the physical page whichincludes the logical page where said to-be-written data is stored,specifies the logical page where data is not stored based on saidvalidity data and treats said specified logical page as said emptylogical page.
 6. The memory device according to claim 5, characterizedin that said controller discriminates whether or not data stored in eachof said logical pages in to-be-erased memory blocks is valid based onsaid validity data, specifies that logical pages which are located inanother memory blocks and where data is not stored and transfers thatdata which has been discriminated as valid into said specified logicalpages, and erases data stored in said to-be-erased memory blocks.
 7. Thememory device according to claim 6, characterized in that wheninformation for specifying a to-be-read logical page to be read out issupplied to said memory device, said controller specifies saidto-be-read logical page based on said information, reads data from saidspecified to-be-read logical page and sends said read data outside. 8.The memory device according to claim 4, characterized in that wheninformation for specifying a to-be-read logical page to be read out issupplied to said memory device, said controller specifies saidto-be-read logical page based on said information, reads data from saidspecified to-be-read logical page and sends said read data outside.
 9. Amemory managing method of managing a non-volatile memory including aplurality of memory blocks which stores data and each of which iscomprised of one or more physical pages each including one or morelogical pages and a redundancy portion, characterized by comprising thesteps of: writing, when to-be-written data is supplied to said memory,said to-be-written data in that empty logical page in said logical pageswhich is in a data storable state; and discriminating whetherto-be-replaced data to be replaced with said to-be-written data isstored in said logical pages, and writing validity data indicating thatsaid to-be-replaced data is not valid in that physical page whichincludes said logical page that stores said to-be-replaced data, when itis discriminated that said to-be-replaced data is stored in said logicalpage.
 10. The memory managing method according to claim 9, characterizedin that validity data indicating that said written to-be-written data isvalid is written in that physical page which includes the logical pagewhere said to-be-written data is stored, that logical page where data isnot stored is specified based on said validity data and said specifiedlogical page is treated as said empty logical page.
 11. The memorymanaging method according to claim 10, characterized by furthercomprising the steps of: discriminating whether or not data stored ineach of said logical pages in to-be-erased memory blocks is valid basedon said validity data, specifying logical pages which are located inanother memory blocks and where data is not stored, transferring thedata which has been discriminated as valid into said specified logicalpages, and erasing data stored in said to-be-erased memory blocks.
 12. Acomputer-readable medium storing a program for allowing a computer,connected to a non-volatile memory including a plurality of memoryblocks which stores data and each of which is comprised of one or morephysical pages each including one or more logical pages and a redundancyportion, to function to: write, when to-be-written data is supplied tosaid memory, said to-be-written data in that empty logical page in saidlogical pages which is in a data storable state; and discriminatewhether to-be-replaced data to be replaced with said to-be-written datais stored in said logical pages, and write validity data indicating thatsaid to-be-replaced data is not valid in that physical page whichincludes said logical page that stores said to-be-replaced data, when itis discriminated that said to-be-replaced data is stored in said logicalpage.